Fundamentals of Bias Temperature Instability in MOS Transistors by Souvik Mahapatra

Author:Souvik Mahapatra
Language: eng
Format: epub
Publisher: Springer India, New Delhi

Keywords

Compact modelNBTIPBTITrap generationTrappingSionHKMG

4.1 Introduction

It has been discussed in Chap. 1 that Negative Bias Temperature Instability (NBTI) and Positive Bias Temperature Instability (PBTI) are well-known reliability issues respectively for p- and n-channel Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) . NBTI has become an important issue as the industry migrated from conventional Silicon Dioxide (SiO2) to Silicon Oxynitride (SiON) gate insulator technology, and continues to remain as a concern for state-of-the-art High K Metal Gate (HKMG) planar and FinFET technologies. PBTI was never a serious concern for SiO2 and SiON MOSFETs and only became important with the advent of HKMG technology, although PBTI is now perceived to be less of a concern for FinFET devices for sub 22 nm technology nodes. Refer to Chap. 1 for a brief overview of NBTI and PBTI degradation across different technology nodes.

It is now well known that BTI degradation is strongly impacted by the gate insulator process, as discussed in Chaps. 1 and 3 and also in this chapter. Therefore, process optimization is an important exercise to develop BTI resistant technologies. Note that BTI measurements are usually performed at accelerated stress conditions for short time, and it is important to develop suitable models to calculate the degradation at end-of-life (EOL) under normal operating condition. This is the primary objective of a reliability model from the perspective of technology qualification. It is important to note that a good model for any reliability phenomenon must have the following characteristics:(a)It should adhere to the physics of the degradation mechanism.

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